library ieee;
use ieee.std_logic_1164.all;

entity mips is
    port(
    reset, clk, dump: in std_logic;
    instr, pc: out std_logic_vector(31 downto 0)
    );
end mips;

architecture behav of mips is
    component controller
        port(
        Op, Funct: in std_logic_vector(5 downto 0);
        MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump:
        out std_logic;
        AluControl: out std_logic_vector(2 downto 0)
        );
    end component;

    component datapath
        port(
        MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump:
        in std_logic;
        AluControl: in std_logic_vector(2 downto 0);
        dump, clk, reset: in std_logic;
        pc, instr: out std_logic_vector(31 downto 0)
        );
    end component;

    signal MTR_s, MW_s, Br_s, AS_s, RD_s, RW_s, Jmp_s: std_logic;
    signal AC_s: std_logic_vector(2 downto 0);
    signal pc_s, instr_s: std_logic_vector(31 downto 0);

begin
    Ctrl0: controller port map(instr_s(31 downto 26), instr_s(5 downto 0),
           MTR_s, MW_s, Br_s, AS_s, RD_s, RW_s, Jmp_s, AC_s);
    Dpath0: datapath port map(MTR_s, MW_s, Br_s, AS_s, RD_s, RW_s, Jmp_s, AC_s,
            dump, clk, reset, pc_s, instr_s);

    instr <= instr_s;
    pc <= pc_s;
end behav;
